Reducing storage data transfer interference with processor power management
US7373534B2 · kind B2 · utility
2Cited by
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14Claims
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Key dates
| Filing date | Jun 23, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Aug 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.