Integrated packet bit error rate tester for 10G SERDES
US7373561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and is connectable to the channel under test. An interface is used for programming the packet transmit and packet receive circuits. The packet transmit circuit can generate an arbitrary 10G SERDES packet in response to commands from the interface. The packet receive circuit can determine a bit error rate of the channel under test. The second memory can capture received packet data upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, and (c) after an error is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.