Post-silicon test coverage verification
US7373619B2 · kind B2 · utility
9Cited by
1References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | May 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31835
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, the invention is directed to a method of optimizing post-silicon test coverage for a system under test (“SUT”). The method comprises defining coverage data comprising Hardware Description Language (“HDL”) events; testing the SUT using a system exerciser connected to the SUT; comparing the results of the testing with the coverage data to identify underutilized areas of functionality of the SUT; and responsive to the comparing operation, performing additional tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.