Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
US7373627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | May 13, 2008 |
| Priority date | — |
| Expiry date | Sep 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) for the wiring structure, a tolerance (ξC) for the capacitance variation ratio (ΔC/C), and a tolerance (ξRC) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=CF/CP) according to a fringe capacitance CF and parallel-plate capacitance CP of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following:The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.