System and method for exposure of partial edge die
US7374866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Feb 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70558
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer. The wafer includes an array of die that includes a plurality of complete die and at least one partial edge die. The wafer has an edge that has a substantially rounded profile causing undersized patterns in semiconductor devices formed on partial edge die. A first exposure intensity is assigned to a first group of die on the surface of the wafer. The first group of die includes a group of complete die, and the first exposure intensity is assigned based at least in part on the location of the first group of die on the surface of the wafer. A second exposure intensity is assigned to a second group of die on the surface of the wafer. The second group of die includes at least one partial edge die. The second exposure intensity less than the first exposure intensity to compensate for reduced line width due to the wafer edge topography. Energy is directed at the second group of die at the second exposure intensity to avoid over-exposure of the second group of die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.