Thin film transistor array panel
US7375373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.