Method and apparatus for increasing stability of MOS memory cells
US7375402B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Nov 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method and apparatus using a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.