Phase locked system for generating distributed clocks
US7375562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.