Robust false locking prevention in referenceless frequency acquisition
US7375591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Sep 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input data stream are determined at least in part according to a bit error rate. The bit error rate is based on transitions of the input data stream occurring in an error zone, the error zone being a predefined phase zone of a sample clock sampling the input data stream. When two control settings that cause the oscillator to lock or false lock are in a same locking region based on proximity of the control settings to each other, a preferred control setting is determined between the two according to respective values of the two control settings. True lock settings are distinguished from false lock settings based on an evaluation of bit errors that occur in an expanded error zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.