DRAM concurrent writing and sensing scheme
US7376027B1 · kind B1 · utility
5Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2006 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Nov 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.