Method and/or architecture implemented in hardware for the adjustment of messages with indeterministic length
US7376152B2 · kind B2 · utility
2Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.