Method for forming variable length instructions in a processing system
US7376814B1 · kind B1 · utility
4Cited by
15References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the number of parameters in the instruction, and definitive characteristics of the parameters. The parameters may represent data which is compressible, thereby enabling the size of parameters in an instruction to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.