Methods of computer power status management and computers utilizing the same
US7376850B2 · kind B2 · utility
2Cited by
2References
31Claims
0Family size
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Key dates
| Filing date | Jul 14, 2005 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Sep 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of computer power state management. When an operating system thereof is idle and the processor thereof transits to a clock-suspended power state (C3/C4 state), an arbitrary bit is asserted to prevent requests from being passed through the Northbridge. When the processor is in the C3/C4 state, if a break event is received, the Southbridge transmits the break event to the Northbridge and changes the processor state from C3/C4 to C0 simultaneously. The break event is subsequently transmitted to the processor when the arbitrary bit is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.