Testing embedded memory in integrated circuits such as programmable logic devices
US7376872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIST engine retrieves the test vectors from the embedded memories and compares them to corresponding expected test vectors supplied by the external tester. Based upon the comparison, the on-chip partial BIST engine forms comparison results indicating whether the retrieved test vectors differ from the corresponding expected test vectors. For programmable logic devices, a full BIST engine may be configured in the integrated circuit for generating the test vectors on chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.