Method for fast ECC memory testing by software including ECC check byte
US7376887B2 · kind B2 · utility
1Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.