Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same
US7376915B1 · kind B1 · utility
4Cited by
6References
7Claims
0Family size
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Key dates
| Filing date | Oct 7, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.