Methods for placement which maintain optimized behavior, while improving wireability potential
US7376924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2005 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Jul 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.