Method for providing layout design and photo mask
US7376931B2 · kind B2 · utility
177Cited by
5References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | May 20, 2008 |
| Priority date | — |
| Expiry date | Feb 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.