Wafer matching methods for use in assembling micromirror array devices
US7378287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Nov 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67288
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for matching micromirror wafers and electrode wafers so as to form micromirror array devices while the production yield is maximized. Each micromirror wafer and/or electrode wafer may have one or more non-passing dies and a plurality of good dies. A set of matching schemes are defined for matching each micromirror wafer with an electrode wafer. For each matching scheme, a cost is calculated with the cost being defined as a total number of unmatched die assemblies resulted from the matching scheme, wherein the unmatched die assembly is defined as an assembly consisting of a passing and non-passing die. Then a matching scheme is selected from the defined matching scheme such that the calculated cost is the minimum among the calculated costs of the defined matching schemes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.