Cleaving process to fabricate multilayered substrates using low implantation doses
US7378330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2006 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Mar 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane. The method also includes providing selected energy to the donor substrate to cleave the device layer from the cleave layer at the cleave plane, whereupon the selected energy i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.