Single-poly EEPROM cell with lightly doped MOS capacitors
US7378705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.