Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
US7378867B1 · kind B1 · utility
3Cited by
154References
6Claims
0Family size
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Key dates
| Filing date | Oct 10, 2006 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017581
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.