System and method for minimizing DC offset in outputs of audio power amplifiers
US7378903B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Jul 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier system receives an input signal and generating therefrom an amplified output signal. The amplifier system is recited as comprising an input stage and an amplifier stage. The input stage is configured to receive the input signal and provide a level-shifted signal that has an average signal level that is shifted in regards a level shift value. The amplifier stage is configured to receive the level-shifted input signal from the input stage and generate therefrom the amplified output signal. The level shift value being selected to minimize a DC offset in the amplified output signal at least when the amplifier system is initially powered on. Since the amplified output signal has a minimal or zero DC offset, the amplifier system avoids generation of undesirable noises when it is initially powered on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.