Method and device for reducing scheduling delay in a digital communication system
US7379863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2003 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W56/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and device within a speech processing unit (SPU) for reducing scheduling delay between the SPU and a radio network node. Within the SPU, data packets are processed in a plurality of time slots that are subunits of frames. The device receives timing information from the node that identifies a beginning and an ending of processing periods in the node. The timing information is utilized to select a time slot within each frame as a target time slot. The target time slot has a position within each frame such that the scheduling delay between the ending of a processing period in the node and the beginning of the target time slot is minimized. Data packets for a particular channel are assigned to the target time slot to reduce the scheduling delay. The phase of the frame is then adjusted by erasing superfluous data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.