Priority registers for biasing access to shared resources
US7380038B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Jul 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their own local resources, they must compete for shared resources. These shared resources may be stored on the chip or off the chip. The priority register biases the arbitration process that arbitrates access to or ongoing use of the shared resources based on the values stored in the priority registers. The way it accomplishes such biasing is by tagging operations issued from the multiple processor cores with the priority values, and then comparing the values within each arbiter of the shared resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.