Method of associating timing violations with critical structures in an integrated circuit design
US7380228B2 · kind B2 · utility
5Cited by
20References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2004 |
| Grant date | May 27, 2008 |
| Priority date | — |
| Expiry date | Nov 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.