Method and apparatus for universal program controlled bus architecture
US7382156B2 · kind B2 · utility
43Cited by
89References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Oct 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.