High voltage input buffer
US7382159B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer circuit includes a voltage limiting circuit and a protection circuit coupled between a pull-up component and a pull-down component of a level detecting circuit. The voltage limiting circuit receives an input signal at a first voltage range and limits the input signal to a safe voltage range, the first voltage range being between an electrical ground and a first supply voltage level, and the safe voltage range being between the electrical ground and a second supply voltage level. The level detecting circuit has a pull-up component receiving the input signal directly from the input terminal and a pull-down component receiving the safe voltage range from the voltage limiting circuit. The level detecting circuit transitions the input signal from the first voltage range to the input signal at the second voltage range. The protection circuit is coupled in series between the pull-up component and the pull-down component so as to protect the level detecting circuit from gate oxide overstress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.