Shift register for pulse-cut clock signal
US7382347B2 · kind B2 · utility
34Cited by
10References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a voltage level of a pulse-cut first clock signal inputted to a first clock terminal is reversed in the state where a first transistor is turned on and a second transistor is turned off, an anti-reversal circuit including a seventh transistor and an eighth transistor supplies a high voltage VDD to a node n2. In this way, a floating state of the node n2 is avoided, and the voltage level of the node n2 is prevented from being reversed. Accordingly, the second transistor will not be turned on in the interval, whereby electric potential of an output signal is stably maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.