Shift register
US7382348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register having an amorphous silicon thin film transistor for decreasing a distortion of the output signal is disclosed. In the shift register having a plurality of stages for shifting an input signal using first and second driving voltages, first and second clock signals and a start pulse, each of said plurality of stages includes an output buffer for selectively applying any one of the first and second clock signals and the second driving voltage to an output line under control of first and second nodes; a pre-charger for pre-charging the first driving voltage into the first node in response to said start pulse; a second node controller for selectively supplying the first and second driving voltages to the second node in such a manner to be opposite to the first node using said start pulse and an output signal of the next stage; and a first node controller for supplying the second driving voltage to the first node in a time interval excluding the time interval for said pre-charging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.