Full-stress testable memory device having an open bit line architecture and method of testing the same
US7382668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Mar 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.