Method and device for reducing high frequency error components of a multi-channel modulator
US7382887B2 · kind B2 · utility
4Cited by
7References
23Claims
0Family size
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Key dates
| Filing date | Apr 23, 2003 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Feb 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R5/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and device for reducing error components of a multi-channel modulator. The method comprises the steps of inverting substantially half of the channels of a modulator, and reducing error components between said inverted channels and said non inverted channels by inductive and/or capacitive summing. The method is especially suitable for synchronized pulses and similar signals to be modulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.