Fast bus image coprocessing
US7382940B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An inspection system having a sensor array that provides image data. A process node includes a memory to receive the image data, a commercially available central processing unit to receive and coprocess at least a first portion of the image data within the memory, and a field programmable gate array to receive and coprocess at least a second portion of the image data within the memory. In this manner, there are two elements in the process node that are used to simultaneously process the image data, and the image data analysis thereby proceeds at a much faster rate than it would with just a single processor in a commercially available computer. However, the system as described has very little custom hardware, and thus is relatively inexpensive, and highly versatile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.