Massively reduced instruction set processor
US7383425B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Apr 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/342
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.