Method and apparatus for designing circuits using high-level synthesis
US7383529B2 · kind B2 · utility
24Cited by
3References
8Claims
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Key dates
| Filing date | Feb 14, 2005 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.