Methods of fabricating flash memory devices including word lines with parallel sidewalls
US7384845B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2004 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | May 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Methods of fabricating integrated circuit devices are provided. The method includes forming a buried diffusion layer in a source active region. A word line pattern is formed crossing over parallel cell active regions and the source active region. The word line pattern has parallel sidewalls such that the word line pattern forms a substantially straight line pattern on an integrated circuit substrate. A plurality of bit line contact plugs and at least one common source contact plug are formed in an insulating layer on the integrated circuit substrate. The bit line contact plugs and the common source contact plug are electrically coupled to the buried diffusion layer and disposed in a line on the integrated circuit substrate that is substantially parallel to the word line pattern. Related integrated circuit devices are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.