Level shifter with reduced power consumption
US7385441B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit has a first transistor and a second transistor in a cascode, and a buffer switch coupled from an output of the buffer to a gate of the second transistor. The buffer circuit is bootstrapped by a bootstrap capacitor, a diode circuit, and a bootstrap switch. The bootstrap capacitor is coupled from the output to the gate of the second transistor through the bootstrap switch. A potential difference is set up across the bootstrap capacitor through the diode circuit. When a low input is given to the buffer circuit, the second transistor turns off and the output goes to a high bias voltage through the first transistor. When a high input is given, the first transistor turns off, the second transistor turns on, and as the output goes low, the gate of the second transistor is bootstrapped to drop the output completely down to a low bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.