Non-volatile, static random access memory with regulated erase saturation and program window
US7385857B2 · kind B2 · utility
6Cited by
2References
18Claims
0Family size
Inventor
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for regulating the erase saturation in a semiconductor memory is disclosed. More particularly, the present invention measures the under-erase and over-erase condition of all SONOS transistors in an array of non-volatile SRAM cells and corrects the erase voltage to prevent over-erase and under-erase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.