Synchronization circuit for DDR IO interface
US7385861B1 · kind B1 · utility
17Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Aug 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first strobe signal having an unknown phase in relation to a local clock signal when receiving data from a memory. The second circuit may be configured to synchronize the first strobe signal with the local clock signal by (i) generating one or more second strobe signals and (ii) inserting a predetermined cycle delay between the one or more second strobe signals and the local clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.