Packet processing system architecture and method
US7385984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jul 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/901
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processing system architecture and method are provided. According to a first aspect of the invention, a plurality of quality of service indicators are provided for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the quality of service indicators for assigning to the packet. According to a second aspect of the invention, wide data paths are utilized in selected areas of the system, while avoiding universal utilization of the wide data paths in the system. According to a third aspect of the invention, one or more stacks are utilized to facilitate packet processing. According to a fourth aspect of the invention, a packet size determiner is allocated to a packet from a pool of packet size determiners, and is returned to the pool upon or after determining the size of the packet. According to a fifth aspect of the invention, a packet is buffered upon or after ingress thereof to the system, and a packet for egress from the system assembled from new or modified packet data and unmodified packet data as retrieved directly from the buffer. According to a sixth aspect of the invention, a system for preventing re-ord…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.