Parallel data link layer controllers in a network switching device
US7385985B2 · kind B2 · utility
12Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | May 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/503
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not possess such functionality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.