Data distribution apparatus and method
US7385996B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2003 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Nov 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A decoding system (1) is provided in which a memory transfer block (14) stores an input transport stream into a memory (16) and the top address of each TS packet into an address memory (15), a CPU (21) refers to information stored in the address memory (15) to access each packet in a memory (16) and analyze header information in the packet, the CPU (21) generates a transfer instruction to transfer data from the memory (16) to a decoder (19 or 20) for each access unit (one frame, for example) and supplies it to a DMA circuit (17 or 18), and the DMA circuit (17 or 18) reads the data from the memory (16) and transfers it to the decoder (19 or 20) according to the transfer instruction supplied from the CPU (21).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.