Phase comparator having a flip-flop circuit and a logic circuit
US7386083B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2003 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase comparator has a flip-flop circuit and a logic circuit. The flip-flop circuit compares an input clock signal with a leading edge and a trailing edge of an input data signal to produce a leading phase comparison result signal indicative of a leading phase comparison result related to the leading edge of the input data signal and a trailing phase comparison result signal indicative of a trailing phase comparison result related to the trailing edge of the input data signal. The logic circuit produces an output up signal when both of the leading and the trailing phase comparison result signals indicate a lag phase of the input clock signal. The logic circuit produces an output down signal when both of the leading and the trailing phase comparison result signals indicate a lead phase of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.