Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding

US7386691B2 · kind B2 · utility

Assignees

• STMICROELECTRONICS N.V. · NL
• STMicroelectronics SA

Inventors

• Friedbert Berens · Geneva, CH
• Michael Thul · Kaiserslautern, DE
• Franck Gilbert · Kaiserslautern, DE
• Norbert Wehn · Queidersbach, DE

Key dates

• Filing date: Apr 13, 2005
• Grant date: Jun 10, 2008
• Expiry date: Dec 7, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M13/2771
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.