Programmable bit error rate monitor for serial interface
US7386767B1 · kind B1 · utility
7Cited by
11References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2004 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jun 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.