Simultaneous timing-driven floorplanning and placement for heterogeneous field programmable gate array
US7386822B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing-driven simultaneous placement and floorplanning method based on a multi-layer density system for heterogeneous field programmable gate arrays are disclosed. The field programmable gate arrays are designed with heterogeneous resources including look-up tables, memory blocks and dedicated logic blocks. Each layer in the multi-layer density system is modeled with a different architectural resource. The placement of look-up tables and the floorplan of computational blocks are concurrently determined in the multi-layer density system. A dynamic timing optimization scheme is also seamlessly integrated in the placement process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.