Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions
US7386844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.