Dual depth trench termination method for improving Cu-based interconnect integrity
US7387960B2 · kind B2 · utility
1Cited by
4References
4Claims
0Family size
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Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Oct 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge α of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150), (160) to form the interconnect line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.