Encapsulated electronic component and production method

US7388281B2 · kind B2 · utility

Assignee

• EPCOS AG · DE

Inventors

• Hans Krueger · Munich, DE
• Jürgen Portmann · Munich, DE
• Karl Nicolaus · Munich, DE
• Gregor Feiertag · Munich, DE
• Alois Stelzl · Munich, DE

Key dates

• Filing date: Jun 23, 2003
• Grant date: Jun 17, 2008
• Expiry date: Jul 14, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/49146
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present invention relates to an encapsulated component that includes a carrier substrate and at least one chip positioned on the top of the carrier substrate and electrically connected to it by means of electrically conductive connections. The encapsulation of the chip is accomplished with a seal or dielectric layer. As a result of differing coefficients of expansion of the seal or dielectric layer and the electrically conductive connections, with changing temperatures stresses occur in the electrically conductive connections, which can lead to cracks, breaks and even to interruption of the electrically conductive connections. To mechanically relieve the electrically conductive connections of stresses from changing temperatures (in particular under extreme thermal loads), it is proposed that the carrier substrate be provided with a support element that encircles the chip, which serves to support the seal or dielectric layer, and/or that the material and the arrangement of the encapsulation be selected accordingly.