Variable delay clock synthesizer
US7388407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2007 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Sep 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a fine resolution of variable clock delay is implemented using a variable DC offset having fine resolution. The proportional ratio between the DC offset and the phase delay/advance of the clock is calibrated in a closed-loop manner. In another embodiment, in a calibration circuit, an adaptive positive DC offset is added to the output of a delay buffer to advance the phase of the clock output, which also has a phase delay from the delay buffer. The DC offset is adjusted in a closed-loop manner to make the phase advance, due to the DC offset, compensate for the phase delay, due to the delay buffer. Once the phase relationship of the DC offset to the clock phase advance is calibrated, the DC offset can be scaled and added to the output of another buffer of the same type to achieve a desired phase delay or advance of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.